How to simulate 2 to 1 mux with vdd and gnd

How to simulate 2 to 1 mux with vdd and gnd

How to simulate 2 to 1 mux with vdd and gnd

On the only hand, a few common sense issues in no way appear to head away. On the opposite hand, those issues can “preserve on giving” in terms of their cap potential to train us matters. How to simulate 2 to 1 mux with vdd and gnd

Recently, I penned a column Logic vdd Gates, Truth Tables, and Karnaugh Maps, Oh My! In this column, we mentioned a PCB Etching Tank common sense hassle that a pupil had published to the EEWeb Forums.

Using 8:1 Multiplexers to Implement Logical Functions

From this, the usage of the Karnaugh map minimization strategies mentioned in my aforementioned column, we ended up with the subsequent common sense circuit and Boolean equation:

Logic circuit and Boolean equation.

I concept we`d positioned this to sleep, till a friend of mine despatched me the subsequent message:

Hi Max, I loved your “Logic Gates, Truth Tables, and Karnaugh Maps, Oh My!” article. Attached is a one-chip approach to the PCB Etching Tank hassle. It will paint for any common sense mixture of the 3 inputs, and it`s smooth to head from the fact desk to the circuit diagram.

It makes use of a CD4512, which has A, B, and C inputs that selects one of 8 statistics inputs (D0 to D7) and provides the country of the chosen enter at the Q output. All you want to do is join the 8 inputs to GND (Ground) or VDD to healthy the 0s and 1s of the Q output of the fact desk.

This message changed into a followed-through diagram proven below. I changed into going to say my buddy`s call here (he gave me his permission), however, I determined to withhold it due to the fact he made an eensy-weensy mistake. We will talk about this slipup in a second, however, first, let`s have a take observe the diagram he despatched me:

Note that that is an INCORRECT implementation

I wasn`t au fait with the CD4512 off the pinnacle of my head, so I had a brief Google even as no person changed into searching and positioned this statistics sheet. The following is my interpretation of the statistics sheet`s fact desk with the pin names barely changed to healthy the chip diagram proven above:

What this tells us is that the CD4512 is an 8:1 multiplexer.

 The 3 choice inputs, A, B, and C are used to pick out one of the 8 D0 to D7 statistics inputs. Whatever common sense fee is on the chosen entry may be offered at the Q output.

We additionally see that there are extra manage pins. A 1 at the active-excessive INH (“inhibit”) will pressure the output to a zero. Meanwhile, a 1 at the active low!OE (“output enable”; I can`t draw the bar over this sign on this text) will disable the output and purpose it to go into an excessive impedance (Z) country.

If we forget about the INH and ! OE indicators for the second, we will constitute the capability of the rest of the chip as a cascade of 2:1 multiplexers as illustrated below:

CD4512 middle capability predicted as a cascade of 2:1 multiplexers

Now, take a second to refer lower back to my buddy`s implementation. What he`s carried out is to hard-cord the D0 to D7 inputs to the zero and 1 values similar to the Q output from our authentic fact desk as illustrated below:

Using 8:1 Multiplexers to Implement Logical Functions

This is a completely tasty solution. We will use our 8:1 multiplexer to put into effect any 3-enter logical function. All we need to do is cord the D0 to D7 inputs to the 0s and 1s we want to see at the Q output as illustrated through the favored fact desk.

The handiest hassle, as I referred to before, is that my buddy made a small error. Before we continue further, you could need to take a second to mirror the stuff we`ve checked out to this point to look if you may spot the hassle.

It may also assist if we examine the favored fact desk from our hassle to the fact desk from the CD4512 statistics sheet as illustrated below:

Do you notice it yet?

 In the case of our authentic desk, we`ve prepared the values similar to the A, B, and C inputs as a fashionable binary count, with A representing the most-extensive bit (MSB) and C representing the least-extensive bit (LSB). By comparison, withinside the case of the CD4512 fact desk, the A enter represents the LSB of the binary count.

As an aside, Elizabeth Simon has been writing a mini-collection of articles describing hints and hints concerning the analysis of statistics sheets (see How to Read Data Sheets: Zener Diodes; additionally Schottky Diodes, Bridge Rectifiers, Rectifier Diodes, and Linear Regulators Part 1 and Part 2). I`m hoping that Elizabeth will cowl statistics sheets for common sense gadgets in her destiny columns.

There are approaches wherein we will cope with this hassle. The first is to change the manner wherein our circuit`s A, B, and C indicators are related to the chip`s A, B, and C inputs (are you able to spot the opportunity solution?). To position this in any other manner, we presently have our circuit indicators A, B, and C related to the chip`s A, B, and C inputs, respectively. What we want to do is join our circuit`s A, B, and C indicators to the chip`s C, B, and A inputs, respectively, as illustrated below:

Using 8:1 Multiplexers to Implement Logical Functions

Pretty cool, eh? But now let`s take matters up a notch. The pupil who posed the authentic hassle published a follow-up question. We won`t cross into this element here. Suffice it to mention that we ended up with the fact desk and circuit diagram illustrated below:

Truth tables and circuit diagrams.

Earlier, we stated that we will use the CD4512`s 8:1 multiplexer to put into effect any 3-enter logical function. In this case, however, we’ve got a 4-enter function. How to simulate 2 to 1 mux with vdd and gnd

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Michael Caine

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